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general description the max5893 programmable interpolating, modulating, 500msps, dual digital-to-analog converter (dac) offers superior dynamic performance and is optimized for high- performance wideband, single-carrier transmit applica- tions. the device integrates a selectable 2x/4x/8x interpolating filter, a digital quadrature modulator, and dual 12-bit high-speed dacs on a single integrated cir- cuit. at 30mhz output frequency and 500msps update rate, the in-band sfdr is 84dbc while consuming 1.1w. the device also delivers 72db aclr for single-carrier wcdma at a 61.44mhz output frequency. the selectable interpolating filters allow lower input data rates while taking advantage of the high dac update rates. these linear-phase interpolation filters ease reconstruction filter requirements and enhance the passband dynamic performance. individual offset and gain programmability allow the user to calibrate out local oscillator (lo) feedthrough and sideband suppression errors generated by analog quadrature modulators. the max5893 features a f im / 4 digital image-reject modulator. this modulator generates a quadrature-mod- ulated if signal that can be presented to an analog i/q modulator to complete the upconversion process. a second digital modulation mode allows the signal to be frequency-translated with image pairs at f im / 2 or f im / 4. the max5893 features a standard 1.8v cmos, 3.3v tol- erant data input bus for easy interface. a 3.3v spi port is provided for mode configuration. the programmable modes include the selection of 2x/4x/8x interpolating fil- ters, f im / 2, f im / 4 or no digital quadrature modulation with image rejection, channel gain and offset adjustment, and offset binary or two? complement data interface. pin-compatible 14- and 16-bit devices are also available. refer to the MAX5894** data sheet for the 14-bit version and the max5895 data sheet for the 16-bit version. applications base stations: 3g umts, cdma, and gsm broadband wireless transmitters broadband cable infrastructure instrumentation and automatic test equipment (ate) analog quadrature modulation architectures features ? 72db aclr at f out = 61.44mhz (single-carrier wcdma) ? meets 3g umts, cdma2000 , gsm spectral masks (f out = 122mhz) ? noise spectral density = -151dbfs/hz at f out = 16mhz ? 90dbc sfdr at low-if frequency (10mhz) ? 86dbc sfdr at high-if frequency (50mhz) ? low power: 511mw (f clk = 100mhz) ? user programmable selectable 2x, 4x, or 8x interpolating filters <0.01db passband ripple >99db stopband rejection selectable real or complex modulator operation selectable modulator lo frequency: off, f im / 2, or f im / 4 selectable output filter: lowpass or highpass channel gain and offset adjustment ? ev kit available (order the max5895evkit) max5893 12-bit, 500msps interpolating and modulating dual dac with cmos inputs ________________________________________________________________ maxim integrated products 1 part resolution (bits) dac update rate (msps) input logic max5893 12 500 cmos MAX5894** 14 500 cmos max5895 16 500 cmos part temp range pin-package pkg code max5893egk -40? to +85? 68 qfn-ep* (10mm x 10mm) g6800-4 selector guide ordering information data synch and demux dac data port a data port b dataclk outi outq modulator 2x interpolating filters 1x/2x/4x interpolating filters dac simplified diagram 19-3546; rev 0; 2/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configuration appears at end of data sheet. spi is a trademark of motorola, inc. cdma2000 is a registered trademark of telecommunications industry association. ** future product?ontact factory for availability. * ep = exposed paddle. evaluation kit available
max5893 12-bit, 500msps interpolating and modulating dual dac with cmos inputs 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (dv dd1.8 = av dd1.8 = 1.8v, av clk = av dd3.3 = dv dd3.3 = 3.3v, modulator off, 2x interpolation, dataclk input mode, dual-port mode, 50 ? double-terminated outputs, external reference at 1.25v, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?, unless otherwise noted.) (note 2) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dv dd1.8 , av dd1.8 to gnd, dacref ..................-0.3v to +2.16v av dd3.3 , av clk , dv dd3.3 to gnd, dacref ........-0.3v to +3.9v dataclk, a0?11, b0?9, seliq/b11, dataclk/b10, cs , reset , sclk, sdi and sdo to gnd, dacref......-0.3v to (dv dd3.3 + 0.3v) clkp, clkn to gnd, dacref..............-0.3v to (av clk + 0.3v) refio, fsadj to gnd, dacref ........-0.3v to (av dd3.3 + 0.3v) outip, outin, outqp, outqn to gnd, dacref..................-1v to (av dd3.3 + 0.3v) sdo, dataclk, dataclk/bio continuous current ..........8ma continuous power dissipation (t a = +70?) 68-pin qfn (derate 41.7mw/? above +70?) (note 1) ...................................................................3333.3mw junction temperature ......................................................+150? operating temperature range ...........................-40? to +85? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? thermal resistance jc (note 1)....................................0.8?/w parameter symbol conditions min typ max units static performance resolution 12 bits differential nonlinearity dnl ?.5 lsb integral nonlinearity inl ? lsb offset error os -0.01 ?.003 +0.01 %fs offset drift ?.03 ppm/? full-scale gain error ge fs -4 ?.6 +4 %fs gain-error drift ?10 ppm/? full-scale output current i outfs 220ma output compliance -0.5 +1.1 v output resistance r out 1m ? output capacitance c out 5pf dynamic performance maximum clock frequency f clk 500 mhz minimum clock frequency f clk 1 mhz maximum dac update rate f dac f dac = f clk or f dac = f clk / 2 500 msps minimum dac update rate f dac f dac = f clk or f dac = f clk / 2 1 msps maximum input data rate f data 125 mwps no interpolation -151 2x interpolation -147 f dataclk = 125mhz, f out = 16mhz, f offset = 10mhz, -12dbfs 4x interpolation -148 noise spectral density f dataclk = 125mhz, f out = 16mhz, f offset = 10mhz, 0dbfs 4x interpolation -145 dbfs/ hz note 1: thermal resistance based on a multilayer board with 4 x 4 via array in exposed paddle area.
max5893 12-bit, 500msps interpolating and modulating dual dac with cmos inputs _______________________________________________________________________________________ 3 electrical characteristics (continued) (dv dd1.8 = av dd1.8 = 1.8v, av clk = av dd3.3 = dv dd3.3 = 3.3v, modulator off, 2x interpolation, dataclk input mode, dual-port mode, 50 ? double-terminated outputs, external reference at 1.25v, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units f out = 10mhz 90 f out = 30mhz 83 f dataclk = 125mhz, interpolation off, 0dbfs f out = 50mhz 72 f out = 10mhz 77 88 f out = 30mhz 83 f dataclk = 125mhz, 2x interpolation, 0dbfs f out = 50mhz 84 f out = 10mhz 90 f out = 30mhz 84 in-band sfdr (dc to f data / 2) sfdr f dataclk = 125mhz, 4x interpolation, 0dbfs f out = 50mhz 86 dbc no interpolation -100 2x interpolation -100 f dataclk = 125mhz, f out1 = 9mhz, f out2 = 10mhz, -6.1dbfs 4x interpolation -100 2x interpolation, f im / 4 complex modulation -73 f data = 125mhz, f out1 = 79mhz, f out2 = 80mhz, -6.1dbfs 4x interpolation, f im / 4 complex modulation -75 f dataclk = 62.5mhz, f out1 = 9mhz, f out2 = 10mhz, -6.1dbfs 8x interpolation -99 f dataclk = 62.5mhz, f out1 = 69mhz, f out2 = 70mhz, -6.1dbfs 8x interpolation, f im / 4 complex modulation -67 two-tone imd ttimd f dataclk = 62.5mhz, f out1 = 179mhz, f out2 = 180mhz, -6.1dbfs 8x, highpass interpolation, f im / 4 complex modulation -62 dbc four-tone imd ftimd f dataclk = 125mhz, f out spaced 1mhz apart from 32mhz, -12dbfs, 2x interpolation -93 dbc 4x interpolation 74 f dataclk = 61.44mhz, f out = baseband 8x interpolation 73 f dataclk = 122.88mhz, f out = 61.44mhz 2x interpolation, f im / 4 complex modulation 73 aclr for wcdma (note 3) aclr f dataclk = 122.88mhz, f out = 122.88mhz 4x interpolation, f im / 4 complex modulation 69 db
max5893 12-bit, 500msps interpolating and modulating dual dac with cmos inputs 4 _______________________________________________________________________________________ electrical characteristics (continued) (dv dd1.8 = av dd1.8 = 1.8v, av clk = av dd3.3 = dv dd3.3 = 3.3v, modulator off, 2x interpolation, dataclk input mode, dual-port mode, 50 ? double-terminated outputs, external reference at 1.25v, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units output propagation delay t pd 1x interpolation (note 4) 2.9 ns output rise time t rise 10% to 90% (note 5) 0.75 ns output fall time t fall 10% to 90% (note 5) 1 ns output settling time to 0.5% (note 5) 11 ns output bandwidth -1db bandwidth (note 6) 240 mhz passband width ripple <-0.01db 0.4 x f data 0.604 x f data , 2x interpolation 100 0.604 x f data , 4x interpolation 100 stopband rejection 0.604 x f data , 8x interpolation 100 db 1x interpolation 22 2x interpolation 70 4x interpolation 146 data latency 8x interpolation 311 clock cycles dac interchannel matching gain match ? gain f out = dc - 80mhz, i outfs = 20ma ?.1 db gain-match tempco ? gain/? i outfs = 20ma ?.02 ppm/? phase match ? phase f out = 60mhz, i outfs = 20ma ?.13 deg phase-match tempco ? phase/? f out = 60mhz, i outfs = 20ma ?.006 deg/? dc gain match i outfs = 20ma -0.2 ?.04 +0.2 db channel-to-channel crosstalk f out = 50mhz, f dac = 250mhz, 0dbfs -90 db reference reference input range 0.125 1.250 v reference output voltage v refio internal reference 1.14 1.20 1.27 v reference input resistance r refio 10 k ? reference voltage drift ?0 ppm/? cmos logic input/output (a11?0, seliq/b11, dataclk/b10, b9?0, dataclk) input high voltage v ih 0.7 x dv dd1.8 v input low voltage v il 0.3 x dv dd1.8 v input current i in ? ?0 ? input capacitance c in 3pf
max5893 12-bit, 500msps interpolating and modulating dual dac with cmos inputs _______________________________________________________________________________________ 5 parameter symbol conditions min typ max units output high voltage v oh 200? load 0.8 x dv dd3.3 v output low voltage v ol 200? load 0.2 x dv dd3.3 v output leakage current three-state 1 a rise/fall time c load = 10pf, 20% to 80% 1.6 ns clock input (clkp, clkn) sine-wave input >1.5 differential input voltage swing v diff square-wave input >0.5 v p-p differential input slew rate >100 v/? common-mode voltage v com ac-coupled av clk / 2 v input resistance r clk 5k ? input capacitance c clk 3pf minimum clock duty cycle 45 % maximum clock duty cycle 55 % clkp/clkn, dataclk timing (figure 4) (note 7) clk to dataclk delay t d dataclk output mode, c load = 10pf 6.2 ns capturing rising edge 1.0 data hold time, dataclk input/output (pin 14) t dh capturing falling edge 2.1 ns capturing rising edge 0.4 data setup time, dataclk input/output (pin 14) t ds capturing falling edge -0.7 ns capturing rising edge 1.0 data hold time, dataclk/b10 input/output (pin 27) t dh capturing falling edge 2.3 ns capturing rising edge 0.2 data setup time, dataclk/b10 input/output (pin 27) t ds capturing falling edge -0.4 ns serial port interface timing (figure 3) (note 7) sclk frequency f sclk 10 mhz cs setup time t ss 2.5 ns input hold time t sdh 0ns input setup time t sds 4.5 ns data valid duration t sdv 6.5 16.5 ns electrical characteristics (continued) (dv dd1.8 = av dd1.8 = 1.8v, av clk = av dd3.3 = dv dd3.3 = 3.3v, modulator off, 2x interpolation, dataclk input mode, dual-port mode, 50 ? double-terminated outputs, external reference at 1.25v, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?, unless otherwise noted.) (note 2)
max5893 12-bit, 500msps interpolating and modulating dual dac with cmos inputs 6 _______________________________________________________________________________________ parameter symbol conditions min typ max units power supplies digital supply voltage dv dd1.8 1.71 1.8 1.89 v digital i/o supply voltage dv dd3.3 3.0 3.3 3.6 v clock supply voltage av clk 3.135 3.3 3.465 v av dd3.3 3.135 3.3 3.465 analog supply voltage av dd1.8 1.71 1.8 1.89 v i avdd3.3 f clk = 100mhz, 2x interpolation, 0dbfs, f out = 10mhz, dataclk output mode 110 130 analog supply current i avdd1.8 f clk = 100mhz, 2x interpolation, 0dbfs, f out = 10mhz, dataclk output mode 10 15 ma digital supply current i dvdd1.8 f clk = 100mhz, 2x interpolation, 0dbfs, f out = 10mhz, dataclk output mode 54 65 ma digital i/o supply current i dvdd3.3 f clk = 100mhz, 2x interpolation, 0dbfs, f out = 10mhz, dataclk output mode 710ma clock supply current i avclk f clk = 100mhz, 2x interpolation, 0dbfs, f out = 10mhz, dataclk output mode 35ma total power dissipation p total 511 mw av dd3.3 450 av dd1.8 1 dv dd1.8 10 dv dd3.3 100 power-down current all i/o are static high or low, bit 2 to bit 4 of address 00h are set high av clk 1 ? av dd3.3 power-supply rejection ratio psrr a (note 8) 0.05 %fs/v electrical characteristics (continued) (dv dd1.8 = av dd1.8 = 1.8v, av clk = av dd3.3 = dv dd3.3 = 3.3v, modulator off, 2x interpolation, dataclk input mode, dual-port mode, 50 ? double-terminated outputs, external reference at 1.25v, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?, unless otherwise noted.) (note 2) note 2: all specifications are 100% tested at t a +25?. specifications at t a < +25? are guaranteed by design and characteriza- tion data. note 3: 3.84mhz bandwidth, single carrier. note 4: excludes data latency. note 5: measured single-ended into a 50 ? load. note 6: excludes sin(x)/x rolloff. note 7: guaranteed by design and characterization. note 8: parameter defined as the change in midscale output caused by a ?% variation in the nominal supply voltage.
max5893 12-bit, 500msps interpolating and modulating dual dac with cmos inputs _______________________________________________________________________________________ 7 in-band sfdr vs. output frequency f data = 125mwps, 2x interpolation max5893 toc01 output frequency (mhz) sfdr (dbc) 40 30 20 10 20 40 60 80 100 120 0 050 -0.1dbfs -6dbfs -12dbfs spurs measured between 0mhz and 62.5mhz 0ut-of-band sfdr vs. output frequency f data = 125mwps, 2x interpolation max5893 toc02 output frequency (mhz) sfdr (dbc) 40 30 20 10 100 0 050 10 20 30 40 50 60 70 80 90 spurs measured between 62.5mhz and 125mhz -0.1dbfs -6dbfs -12dbfs in-band sfdr vs. output frequency f data = 125mwps, 2x interpolation max5893 toc03 output frequency (mhz) sfdr (dbc) 102.5 92.5 82.5 72.5 10 20 30 40 50 60 70 80 90 0 62.5 112.5 upper sideband modulation spurs measured between 62.5mhz and 125mhz -6dbfs -0.1dbfs -12dbfs in-band sfdr vs. output frequency f data = 125mwps, 4x interpolation max5893 toc04 output frequency (mhz) sfdr (dbc) 40 30 20 10 20 40 60 80 100 120 0 050 -0.1dbfs -6dbfs -12dbfs spurs measured between 0mhz and 62.5mhz out-of-band sfdr vs. output frequenc y f data = 125mwps, 4x interpolation max5893 toc05 output frequency (mhz) sfdr (dbc) 40 30 20 10 10 20 30 40 50 60 70 80 90 0 050 spurs measured between 62.5mhz and 250mhz -6dbfs -0.1dbfs -12dbfs in-band sfdr vs. output frequency f data = 125mwps, 4x interpolation max5893 toc06 output frequency (mhz) sfdr (dbc) 115 105 95 85 100 0 75 125 10 20 30 40 50 60 70 80 90 lower sideband modulation spurs measured between 62.5mhz and 125mhz -0.1dbfs -6dbfs -12dbfs in-band sfdr vs. output frequency f data = 125mwps, 4x interpolation max5893 toc07 output frequency (mhz) sfdr (dbc) 165 155 145 135 10 20 30 40 50 60 70 80 90 0 125 175 upper sideband modulation spurs measured between 125mhz and 187.5mhz -6dbfs -0.1dbfs -12dbfs two-tone imd vs. output frequency f data = 125mwps, 2x interpolation max5893 toc08 center frequency (mhz) two-tone imd (-dbc) 100 75 50 25 20 40 60 80 100 120 0 0 1mhz carrier spacing complex modulation for output frequencies greater than 50mhz -12dbfs -6dbfs -9dbfs two-tone imd vs. output frequency f data = 125msps, 4x interpolation max5893 toc09 center frequency (mhz) two-tone imd (-dbc) 150 120 90 60 30 30 60 90 120 0 0 1mhz carrier spacing complex modulation for output frequencies greater than 50mhz -12dbfs -6dbfs -9dbfs typical operating characteristics (dv dd1.8 = av dd1.8 = 1.8v, av clk = av dd3.3 = dv dd3.3 = 3.3v, modulator off, 2x interpolation, output is transformer-coupled to 50 ? load, t a = +25?, unless otherwise noted.)
max5893 12-bit, 500msps interpolating and modulating dual dac with cmos inputs 8 _______________________________________________________________________________________ gain mismatch vs. temperature f data = 125msps, 2x interpolation max5893 toc10 temperature ( c) gain mismatch (db) 60 35 10 -15 0.025 0.050 0.075 0.100 0 -40 85 f out = 22.7mhz a out = -6dbfs differential nonlinearity vs. digital input code max5893 toc11 digital input code dnl (lsb) 3584 3072 2560 2048 1536 1024 512 -0.5 0 0.5 1.0 -1.0 0 4096 integral nonlinearity vs. digital input code max5893 toc12 digital input code inl (lsb) 3584 3072 2560 2048 1536 1024 512 -0.25 0.50 -0.75 0 0.75 -0.50 0.25 1.00 -1.00 0 4096 supply currents vs. dac update rate 2x interpolation, f out = 5mhz max5893 toc13 f dac (mhz) supply current (ma) 250 200 150 50 100 150 200 250 300 350 400 450 500 0 100 300 1.8v total 3.3v total supply currents vs. dac update rate 4x interpolation, f out = 5mhz max5893 toc14 f dac (mhz) supply current (ma) 400 300 200 50 100 150 200 250 300 350 400 450 500 0 100 500 1.8v total 3.3v total supply currents vs. dac update rate 8x interpolation, f out = 5mhz max5893 toc15 f dac (mhz) supply current (ma) 400 300 200 50 100 150 200 250 300 350 400 450 500 0 100 500 1.8v total 3.3v total typical operating characteristics (continued) (dv dd1.8 = av dd1.8 = 1.8v, av clk = av dd3.3 = dv dd3.3 = 3.3v, modulator off, 2x interpolation, output is transformer-coupled to 50 ? load, t a = +25?, unless otherwise noted.)
max5893 12-bit, 500msps interpolating and modulating dual dac with cmos inputs _______________________________________________________________________________________ 9 wcdma aclr spectral plot f data = 122.88mwps, 4x interpolation max5893 toc19 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -120 f center = 122.88mhz span = 25.5mhz aclr2 = 71db output power (dbm) aclr1 = 69db aclr1 = 69db aclr2 = 70db carrier = -14dbm typical operating characteristics (continued) (dv dd1.8 = av dd1.8 = 1.8v, av clk = av dd3.3 = dv dd3.3 = 3.3v, modulator off, 2x interpolation, output is transformer-coupled to 50 ? load, t a = +25?, unless otherwise noted.) wcdma aclr vs. output frequency f data = 122.88mwps, 4x interpolation max5893 toc16 f center (mhz) aclr (db) 120 80 40 50 60 70 80 90 100 40 0 160 single-carrier alternate channel single-carrier adjacent channel wcdma aclr vs. output frequency f data = 76.8mwps, 4x interpolation max5893 toc17 f center (mhz) aclr (db) 80 40 50 60 70 80 90 100 40 0 single-carrier alternate channel single-carrier adjacent channel max5893 toc18 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -120 wcdma aclr spectral plot f data = 61.44mwps, 8x interpolation f center = 61.44mhz span = 25.5mhz aclr2 = 73db output power (dbm) aclr1 = 73db aclr1 = 72db aclr2 = 73db carrier = -12dbm
max5893 12-bit, 500msps interpolating and modulating dual dac with cmos inputs 10 ______________________________________________________________________________________ pin description pin name function 1 clkp noninverting differential clock input 2 clkn inverting differential clock input 3, 4, 5, 22?5, 40?3 n.c. internally connected. do not connect. 6, 21, 30, 37 dv dd1.8 digital power supply. accepts a 1.71v to 1.89v supply range. bypass each pin to ground with a 0.1? capacitor as close to the pin as possible. 7?2, 15?0 a11?0 a-port data inputs. dual-port mode: i-channel data input. data is latched on the rising/falling edge (programmable) of the dataclk. single-port mode: i-channel and q-channel data input, with seliq. 13, 44 dv dd3.3 cmos i/o power supply. accepts a 3.0v to 3.6v supply range. bypass each pin to ground with a 0.1? capacitor as close to the pin as possible. 14 dataclk programmable data clock input/output. see the dataclk modes section for details. 26 seliq/b11 select i/q-channel input or b-port msb input. single-port mode: if seliq = low, data is latched into q-channel on the rising/falling edge (programmable) of the dataclk. if seliq = high, data is latched into i-channel on the rising/falling edge (programmable) of the dataclk. dual-port mode: q-channel msb input. 27 dataclk/b10 alternate dataclk input/output or b-port bit 10 input. single-port mode: see the dataclk modes section for details. dual-port mode: q-channel bit 10 input. if unused connect to gnd. 28, 29, 31?6, 38, 39 b9?0 b-port data bits 9?. dual-port mode: q-channel inputs. data is latched on the rising/falling (programmable) edge of the dataclk. single-port mode: connect to gnd. 45 sdo serial-port data output 46 sdi serial-port data input 47 sclk serial-port clock input. data on sdi is latched on the rising edge of sclk. 48 cs serial-port interface select. drive cs low to enable serial-port interface. 49 reset reset input. set reset low during power-up. 50 refio reference input/output. bypass to ground with a 1? capacitor as close to the pin as possible. 51 dacref c ur r ent- s et resi stor retur n p ath. for a 20m a ful l - scal e outp ut cur r ent, connect a 2k ? r esi stor b etw een fs ad j and d ac re f. inter nal l y connected to gn d . d o no t u s e a s a n e x t e r n a l g r o u n d co n n e c t io n . 52 fsadj full-scale adjust input. this input sets the full-scale output current of the dac. for a 20ma full- scale output current, connect a 2k ? resistor between fsadj and dacref.
max5893 12-bit, 500msps interpolating and modulating dual dac with cmos inputs ______________________________________________________________________________________ 11 pin description (continued) functional diagram pin name function 53, 67 av dd1.8 low analog power supply. accepts a 1.71v to 1.89v supply range. bypass each pin to gnd with a 0.1? capacitor as close to the pin as possible. 54, 56, 59, 61, 64, 66 gnd ground 55, 60, 65 av dd3.3 analog power supply. accepts a 3.135v to 3.465v supply range. bypass each pin to gnd with a 0.1? capacitor as close to the pin as possible. 57 outqn inverting differential dac current output for q-channel 58 outqp noninverting differential dac current output for q-channel 62 outin inverting differential dac current output for i-channel 63 outip noninverting differential dac current output for i-channel 68 av clk clock power supply. accepts a 3.135v to 3.465v supply range. bypass to ground with a 0.1? capacitor as close to the pin as possible. ep gnd exposed pad. must be connected to gnd through a low-impedance path. idac outip outin qdac outqp outqn seliq a0?11 b0?11 dataclk serial interface control registers reference modulator clock buffers and dividers clkp clkn reset f clk f dac f dac data synch and demux mux q i q i 2x interpolating filter 2x interpolating filter 2x interpolating filter 2x interpolating filter 2x interpolating filter 2x interpolating filter mux mux mux digital offset adjust digital offset adjust digital gain adjust /2 /2 sdo sdi cs sclk dacref fsadj refio f im / 2, f im / 4 digital gain adjust /2 /2 max5893
max5893 12-bit, 500msps interpolating and modulating dual dac with cmos inputs 12 ______________________________________________________________________________________ detailed description the max5893 dual, 500msps, high-speed, 12-bit, cur- rent-output dac provides superior performance in communication systems requiring low-distortion ana- log-signal reconstruction. the max5893 combines two dac cores with 8x/4x/2x/1x programmable digital inter- polation filters, a digital quadrature modulator, an spi- compatible serial interface for programming the device, and an on-chip 1.20v reference. the full-scale output current range is programmable from 2ma to 20ma to optimize power dissipation and gain control. each channel contains three selectable interpolating fil- ters making the max5893 capable of 1x, 2x, 4x, or 8x interpolation, which allows for low-input and high-out- put data rates. when operating in 8x interpolation mode, the interpolator increases the dac conversion rate by a factor of eight, providing an eight-fold increase in separation between the reconstructed waveform spectrum and its first image. the max5893 accepts either two? complement or offset binary input data format and can operate from either a single- or dual-port input bus. the max5893 includes modulation modes at f im / 2 and f im / 4, where f im is the data rate at the input of the mod- ulator. if 2x interpolation is used, this data rate is 2x the input data rate. if 4x or 8x interpolation is used, this data rate is 4x the input data rate. table 1 summarizes the modulator operating data rates for dual-port mode. the power-down modes can be used to turn off each dac? output current or the entire digital section. programming both dacs into power-down simultane- ously will automatically power down the digital interpo- lator filters. note the spi section is always active. the analog and digital sections of the max5893 have separate power-supply inputs (av dd3.3 , av dd1.8 , av clk , dv dd3.3 , and dv dd1.8 ), which minimize noise coupling from one supply to the other. av dd1.8 and dv dd1.8 operate from a typical 1.8v supply, and all other supply inputs operate from a typical 3.3v supply. serial interface the spi-compatible serial interface programs the max5893 registers. the serial interface consists of the cs , sdi, sclk, and sdo. data is shifted into sdi on the rising edge of the sclk when cs is low. when cs is high, data presented at sdi is ignored and sdo is in high-impedance mode. note: cs must transition high after each read/write operation. sdo is the serial data output for reading registers to facilitate easy debug- ging during development. sdi and sdo can be con- nected together to form a 3-wire serial interface bus or remain separate and form a 4-wire spi bus. the serial interface supports two-byte transfer in a communication cycle. the first byte is a control byte written to the max5893 only. the second byte is a data byte and can be written to or read from the max5893. table 1. quadrature modulator operating data rates (f im is the data rate at the input of the modulator) for dual-port mode interpolation rate modulation mode (f lo ) modulation frequency relative to f dac modulation frequency relative to f data f im / 2 f dac / 2 f data / 2 1x f im / 4 f dac / 4 f data / 4 f im / 2 f dac / 2 f data 2x f im / 4 f dac / 4 f data / 2 f im / 2 f dac / 2 2 x f data 4x f im / 4 f dac / 4 f data f im / 2 f dac / 4 2 x f data 8x f im / 4 f dac / 8 f data
when writing to the max5893, data is shifted into sdi; data is shifted out of sdo in a read operation. bits 0 to 3 of the control byte are the address bits. these bits set the address of the register to be written to or read from. bits 4 to 6 of the control byte must always be set to 0. bit 7 is a read/write bit: 0 for write operation and 1 for read operation. the most significant bit (msb) is shifted in first in default mode. if the serial port is set to lsb- first mode, both the control byte and data byte are shifted lsb in first. figures 1 and 2 show the spi serial interface operation in the default write and read mode, respectively. figure 3 is a timing diagram for the spi serial interface. max5893 12-bit, 500msps interpolating and modulating dual dac with cmos inputs ______________________________________________________________________________________ 13 figure 1. spi serial interface write cycle, msb-first mode cs sclk sdi sdo 10003210 high impedance ignored address data read cycle n - 1 data n - 2 10003210 high impedance ignored address data read cycle n data n - 1 10003210 high impedance ignored address data read cycle n + 1 data n 0 0 0 0 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 cs sclk sdi sdo high impedance figure 2. spi serial interface read cycle, msb-first mode
max5893 12-bit, 500msps interpolating and modulating dual dac with cmos inputs 14 ______________________________________________________________________________________ t ss sclk sdi t sds t sdh cs t sdv sdo figure 3. spi serial-interface timing diagram
max5893 12-bit, 500msps interpolating and modulating dual dac with cmos inputs ______________________________________________________________________________________ 15 programming registers programming its registers with the spi serial interface sets the max5893 operation modes. table 2 shows all of the registers. the following are descriptions of each register. add bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00h unused 0 = msb first 1 = lsb first software reset 0 = normal 1 = reset all registers interpolator power-down 0 = normal 1 = power-down idac power- down 0 = normal 1 = power-down qdac power- down 0 = normal 1 = power-down unused 01h interpolation rate (bit 7, bit 6) 00 = no interpolation 01 = 2x interpolation 10 = 4x interpolation 11 = 8x interpolation third interpolation filter configuration 0 = lowpass 1 = highpass modulation mode (bit 4, bit 3) 00 = modulation off 01 = f im / 2 10 = f im / 4 11 = f im / 4 mixer modulation mode 0 = complex 1 = real modulation sign 0 = e -j 1 = e +j unused 02h 0 = two? complement input data 1 = offset binary input data 0 = single port (a), interleaved i/q 1 = dual port i/q input 0 = clock output on dataclk 1 = clock output on d atac lk/b10 0 = input data latched on rising clock edge 1 = input data latched on falling clock edge 0 = data clock input enabled 1 = data clock output enabled data synchronizer 0 = enabled 1 = disabled unused 03h unused 04h 8-bit idac fine-gain adjustment (see the gain adjustment section). bit 7 is msb and bit 0 is lsb. default: 00h 05h unused 4-bit idac coarse-gain adjustment (see the gain adjustment section). bit 3 is msb and bit 0 is lsb. default: fh 06h 10-bit idac offset adjustment (see the offset adjustment section). bits 7 to 0 of the 06h register are the msb bits. bit 1 and bit 0 are the lsb bits in 07h register. default: 000h 07h idac ioffset direction 0 = current on outin 1 = current on outip unused idac offset adjustment bit 1 (see 06h register) idac offset adjustment bit 0 (see 06h register) 08h 8-bit qdac fine-gain adjustment (see the gain adjustment section). bit 7 is msb and bit 0 is lsb. default: 00h 09h unused 4-bit qdac coarse-gain adjustment (see the gain adjustment section). bit 3 is msb and bit 0 is lsb. default: fh 0ah 10-bit qdac offset adjustment (see the offset adjustment section). bits 7 to 0 of the 0ah register are the msb bits. bit 1 and bit 0 are the lsb bits in 0bh register. default: 000h 0bh qdac ioffset direction 0 = current on outqn 1 = current on outqp unused qdac offset adjustment bit 1 (see 0ah register) qdac offset adjustment bit 0 (see 0ah register) 0ch reserved, do not write to these bits. 0dh reserved, do not write to these bits. 0eh reserved, do not write to these bits. table 2. max5893 programmable registers conditions in bold are default states after reset.
max5893 12-bit, 500msps interpolating and modulating dual dac with cmos inputs 16 ______________________________________________________________________________________ address 00h bit 6 logic 0 (default) causes the serial port to use msb first address/data format. when set to a logic 1, the serial port will use lsb first address/data format. bit 5 when set to a logic 1, all registers reset to their default state (this bit included). bit 4 logic 1 stops the clock to the digital interpo- lators. dac outputs hold last value prior to interpolator power-down. bit 3 idac power-down mode. a logic 1 to this bit powers down the idac. bit 2 qdac power-down mode. a logic 1 to this bit powers down the qdac. note: if both bit 2 and bit 3 are 1, the max5893 is in full-power-down mode, leaving only the serial interface active. address 01h bits 7, 6 configure the interpolation filters according to the following table: 00 1x (no interpolation) 01 2x 10 4x 11 8x (default) bit 5 logic 0 configures fir3 as a lowpass digital filter (default). a logic 1 configures fir3 as a highpass digital filter. bits 4, 3 configure the modulation frequency accord- ing to the following table: 00 no modulation 01 f im / 2 modulation 10 f im / 4 modulation (default) 11 f im / 4 modulation where f im is the data rate at the input of the modulator. bit 2 configures the modulation mode for either real or complex (image reject) modulation. logic 1 sets the modulator to the real mode (default). complex modulation is only avail- able for f im / 4 modulation. bit 1 quadrature modulator sign inversion. with i- channel data leading q-channel data by 90? logic 0 sets the complex modulation to be e -jw (default), cancelling the upper image when used with an external quadrature mod- ulator. a logic 1 sets the complex modulation to be e +jw , cancelling the lower image when used with an external quadrature modulator. address 02h bit 7 logic 0 (default) configures the data port for two? complement. a logic 1 configures the data ports for offset binary. bit 6 logic 0 (default) configures the data bus for single-port, interleaved i/q data. i and q data enter through one 12-bit bus. logic 1 config- ures the data bus for dual-port i/q data. i and q data enter on separate buses. bit 5 logic 0 (default) configures the data clock for pin 14. a logic 1 configures the data clock for pin 27 (dataclk/b10). bit 4 logic 0 (default) sets the internal latches to latch the data on the rising edge of dataclk. a logic 1 sets the internal latches to latch the data on the falling edge of dataclk. bit 3 logic 0 (default) configures the dataclk pin (pin 14 or pin 27) to be an input. a logic 1 configures the dataclk pin to be an output. bit 2 logic 0 (default) enables the data synchro- nizer circuitry. a logic 1 disables the data synchronizer circuitry. address 03h bits 7? unused. address 04h bits 7? these 8 bits define the binary number for fine-gain adjustment of the idac full-scale current (see the gain adjustment section). bit 7 is the msb. default is all zeros. address 05h bits 3? these four bits define the binary number for the coarse-gain adjustment of the idac full- scale current (see the gain adjustment sec- tion). bit 3 is the msb. default is all ones. address 06h, bits 7 to 0; address 07h, bit 1 and bit 0 these 10 bits represent a binary number that defines the magnitude of the offset added to the idac output (see the offset adjustment section). default is all zeros.
address 07h bit 7 logic 0 (default) adds the 10 bits offset cur- rent to outin. a logic 1 adds the 10 bits off- set current to outip. address 08h bits 7? these 8 bits define the binary number for fine-gain adjustment of the qdac full-scale current (see the gain adjustment section). bit 7 is the msb. default is all zeros. address 09h bits 3? these four bits define the binary number for the coarse-gain adjustment of the qdac full- scale current (see the gain adjustment sec- tion). bit 3 is the msb. default is all ones. address 0ah, bits 7 to 0; address 0bh, bit 1 and bit 0 these 10 bits represent a binary number that defines the magnitude of the offset added to the qdac output (see the offset adjustment section). default is all zeros. address 0bh bit 7 logic 0 (default) adds the 10 bits offset to outqn. a logic 1 adds the 10 bits offset to outqp. offset adjustment offset adjustment is achieved by adding a digital code to the dac inputs. the code offset (see equation below), as stored in the relevant control registers, has a range from 0 to 1023 and a sign bit. the applied dac offset is 4 times the code stored in the register, provid- ing an offset adjustment range of ?55 lsb codes. the resolution is 1 lsb. gain trim gain trimming is done by varying the full-scale current according to the following formula: where i ref is the reference current (see the internal reference section). coarse is the register content of registers 05h and 09h for the i- and q-channel, respec- tively. fine is the register content of register 04h and 08h for the i- and q-channel, respectively. the range of coarse is from 0 to 11, with 11 being the default. the range for fine is from 0 to 255 with 0 being the default. given this, the gain can be adjusted in steps of approx- imately 0.01db. single-port/dual-port data input modes the max5893 is capable of capturing data in single- port and dual-port modes (selected through bit 6, address 02h). in single-port mode, the data for both channels is input through the a port (a11?0). the channel for the input data is determined through the state of the seliq/b11 (pin 26) bit. when seliq is set to logic-high, the input data is presented to the i-channel, when set to logic-low, the input data is presented to the q-channel. the unused b-port inputs (dataclk/b10, b9?0) should be grounded when run- ning in single-port mode. dual-port mode, as the name implies, requires that each channel receives its data from a separate data bus. seliq/b11 and dataclk/b10 revert to data bit inputs for the q-channel in dual-port mode. the max5893 control registers can be programmed to allow either signed or unsigned binary format (bit 7, address 02h) data in either single-port or dual-port mode. table 3 shows the corresponding dac output levels when using signed or unsigned data modes. data synchronization modes data synchronization circuitry is provided to allow oper- ation with an input data clock. the data clock must be frequency locked to the dac clock (f dac ), but can have arbitrary phase with respect to the dac clock. the synchronization circuitry allows for phase jitter on the input data clock of up to ? data clock cycles. synchronization is initially established when the reset pin is asynchronously deasserted and the input data clock has been running for at least 4 clock cycles. subsequently, the max5893 monitors the phase rela- i i coarse i fine outfs ref ref = ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 3 4 1 16 3 32 256 1024 24 i offset i offset outfs = 4 2 16 max5893 12-bit, 500msps interpolating and modulating dual dac with cmos inputs ______________________________________________________________________________________ 17 digital input code offset binary (unsigned) two's complement (signed) out_p out_n 0000 0000 0000 1000 0000 0000 0 i outfs 0111 1111 1111 0000 0000 0000 i outfs / 2 i outfs / 2 1111 1111 1111 0111 1111 1111 i outfs 0 table 3. dac output code table
max5893 tionship and detects if the phase drifts more than ? data clock cycle. if this occurs, the synchronizer auto- matically reestablishes synchronization. however, dur- ing the resynchronization phase, up to 8 data words may be lost or repeated. bit 2 of register 02h disables or enables (default) the automatic data clock phase detection. disabling the data synchronization circuitry requires the data clock and the dac clock phase to be locked. dataclk modes the max5893 has a main dataclk available at pin 14. an alternate dataclk is available at pin 27 (dataclk/b10) when configured in single-port data input mode (bit 5, address 02h). the dataclk can be configured to accept an input clock signal for latching the input data, or to source a clock signal that can drive up to 10pf load while latching the input data (bit 3, address 02h). if dataclk is configured as an output, it is frequency divided from the clkp/clkn input, depending on the operating mode, see table 4. the max5893 can be configured to latch the input data on either the rising edge or falling edge of the dataclk signal (bit 4, address 02h). figure 4 shows the timing requirements between the dataclk signal and the input data bus with latching on the rising edge. 12-bit, 500msps interpolating and modulating dual dac with cmos inputs 18 ______________________________________________________________________________________ input mode interpolation rate f data :f clk f dac :f clk 1x 1:1 1:2 2x 1:1 1:1 4x 1:2 1:1 single port 8x 1:4 1:1 1x 1:1 1:1 2x 1:2 1:1 4x 1:4 1:1 dual port 8x 1:8 1:1 table 4. clock frequency ratios in various modes figure 4. data input timing diagram t d t ds t clk clkp?lkn dataclk a0?11/b0?11 t dh
max5893 12-bit, 500msps interpolating and modulating dual dac with cmos inputs ______________________________________________________________________________________ 19 interpolating filter the max5893 features three cascaded fir half-band filters. the interpolating filters are enabled or disabled in combinations to support 1x (no interpolation), 2x, 4x, or 8x interpolation. bits 7 and 6 of register 01h set the interpolation rate (see table 2). the last interpolation fil- ter is located after the modulator. in the 8x interpolation mode, the last filter (fir3) can be configured as low- pass or highpass (bit 5, address 01h) to select the lower or upper sideband from the modulation output. the frequency responses of these three filters are plot- ted in figures 5?. figure 5. interpolation filter frequency response, 2x interpolation mode 0 0.1 0.2 0.3 0.4 -0.0004 -0.0002 0 passband detail 0 0 0.4 0.6 0.8 f out - normalized to input data rate 1.0 1.2 1.4 1.6 1.8 2.0 -20 -40 -60 -80 -100 gain (dbfs) -120 0.2 0 0.1 0.2 0.3 0.4 -0.0004 -0.0002 0 passband detail figure 6. interpolation filter frequency response, 4x interpolation mode 0 0 1.0 1.5 2.0 f out - normalized to input data rate 2.5 3.0 3.5 4.0 -20 -40 -60 -80 -100 gain (dbfs) -120 0.5 0 0.1 0.2 0.3 0.4 -0.0004 -0.0002 0 passband detail figure 7. interpolation filter frequency response, 8x interpolation mode (fir3 lowpass mode) 0 0234 f out - normalized to input data rate 5678 -20 -40 -60 -80 -100 gain (dbfs) -120 1 0 0.1 0.2 0.3 0.4 -0.0004 -0.0002 0 passband detail figure 8. interpolation filter frequency response, 8x interpolation mode (fir3 highpass mode) 0 0234 f out - normalized to input data rate 5678 -20 -40 -60 -80 -100 gain (dbfs) -120 1 3.6 3.8 4.0 4.2 4.4 -0.0004 -0.0002 0 passband detail
max5893 the programmable interpolation filters multiply the max5893 input data rate by a factor of 2x, 4x, or 8x to separate the reconstructed waveform spectrum and the dac image. the original spectral images, appearing at around multiples of the input data rate, are attenuated by the internal digital filters. this feature provides three benefits: 1) image separation reduces complexity of analog reconstruction filters. 2) lower input data rates eliminate board-level high- speed data transmission. 3) sin(x)/x rolloff is reduced over the effective bandwidth. figure 9 illustrates a practical example of the benefits when using the max5893 in 2x, 4x, and 8x interpolation modes with the third filter configured as a lowpass filter. with no interpolation filter, the first image signal appears in the second nyquist zone between f s / 2 and f s . the first interpolating filter removes this image. in fact, all of the 12-bit, 500msps interpolating and modulating dual dac with cmos inputs 20 ______________________________________________________________________________________ figure 9. spectral representation of interpolating filter responses (output frequencies are relative to the data input frequency , f s ) f s 2f s 3f s 4f s 5f s 6f s 7f s 8f s f s 2f s 3f s 4f s 5f s 6f s 7f s 8f s f s 2f s 3f s 4f s 5f s 6f s 7f s 8f s f s 2f s 3f s 4f s 5f s 6f s 7f s 8f s f s 2f s 3f s 4f s 5f s 6f s 7f s 8f s f s 2f s 3f s 4f s 5f s 6f s 7f s 8f s filter response filter response filter response input spectrum and first filter response output spectrum of the first filter input spectrum and second filter response output spectrum of the second filter input spectrum and third filter response output spectrum of the third filter 2x interpolation 4x interpolation 8x interpolation no interpolation signal image signal image signal image signal signal signal image image image
images at odd numbers of f s are filtered. at the output of the first filter, the images are at 2f s , 4f s , etc. this signal is then passed to the second interpolating filter, which is similar to the first filter and removes the images at 2f s , 6f s , 10f s , etc. finally, the third filter removes images at 4f s , 12f s , 20f s , etc. figures 10, 11, and 12 similarly illustrate the spectral responses when using the interpolating filters combined with the digital modulator. max5893 12-bit, 500msps interpolating and modulating dual dac with cmos inputs ______________________________________________________________________________________ 21 figure 10. spectral representation of 4x interpolation filter with f im / 4 modulation (output frequencies are relative to the data input frequency, f s ) for complex modulation the modulation sign (bit 1, address 01h) selects upper or lower sideband lower sideband upper sideband f s 2f s 3f s 4f s f s 2f s 3f s 4f s f s 2f s 3f s 4f s f s 2f s 3f s 4f s f s 2f s 3f s 4f s filter response filter response input spectrum and first filter response output spectrum of the first filter input spectrum and second filter response output spectrum of the second filter output spectrum of the modulator 2x interpolation 4x interpolation no interpolation signal image signal image signal image signal signal image image
max5893 12-bit, 500msps interpolating and modulating dual dac with cmos inputs 22 ______________________________________________________________________________________ figure 11. spectral representation of 8x interpolation filter with f im / 4 modulation and lowpass mode enabled (output frequencies are relative to the data input frequency, f s ) f s 2f s 3f s 4f s 5f s 6f s 7f s 8f s f s 2f s 3f s 4f s 5f s 6f s 7f s 8f s f s 2f s 3f s 4f s 5f s 6f s 7f s 8f s f s 2f s 3f s 4f s 5f s 6f s 7f s 8f s f s 2f s 3f s 4f s 5f s 6f s 7f s 8f s f s 2f s 3f s 4f s 5f s 6f s 7f s 8f s filter response filter response input spectrum and first filter response output spectrum of the first filter input spectrum and second filter response output spectrum of the second filter output spectrum of the modulator output spectrum of the third filter 2x interpolation 4x interpolation 8x interpolation no interpolation signal image signal image signal image signal signal image image image image f s 2f s 3f s 4f s 5f s 6f s 7f s 8f s filter response input spectrum and third filter response signal for complex modulation the modulation sign (bit 1, address 01h) selects upper or lower sideband lower sideband upper sideband signal
max5893 12-bit, 500msps interpolating and modulating dual dac with cmos inputs ______________________________________________________________________________________ 23 figure 12. spectral representation of 8x interpolation filter with f im / 4 modulation and highpass mode enabled (output frequencies are relative to the data input frequency, f s ) f s 2f s 3f s 4f s 5f s 6f s 7f s 8f s f s 2f s 3f s 4f s 5f s 6f s 7f s 8f s f s 2f s 3f s 4f s 5f s 6f s 7f s 8f s f s 2f s 3f s 4f s 5f s 6f s 7f s 8f s f s 2f s 3f s 4f s 5f s 6f s 7f s 8f s f s 2f s 3f s 4f s 5f s 6f s 7f s 8f s filter response filter response input spectrum and first filter response output spectrum of the first filter input spectrum and second filter response output spectrum of the second filter output spectrum of the modulator output spectrum of the third filter 2x interpolation 4x interpolation 8x interpolation no interpolation signal image signal image signal image signal signal image image image image f s 2f s 3f s 4f s 5f s 6f s 7f s 8f s filter response input spectrum and third filter response signal for complex modulation the modulation sign (bit 1, address 01h) selects upper or lower sideband lower sideband upper sideband signal
max5893 digital modulator the max5893 features digital modulation at frequen- cies of f im / 2 and f im / 4, where f im is the data rate at the input to the modulator. f im equals f dac in 1x, 2x, and 4x interpolation modes. in 8x interpolation mode, f im equals f dac / 2. the output rate of the modulator is always the same as the input data rate to the modula- tor, f im . in complex modulation mode, data from the second interpolation filter is frequency mixed with the on-chip in-phase and quadrature (i/q) local oscillator (lo). complex modulation provides the benefit of image sideband rejection when combined with an external quadrature modulator commonly found in wireless communication systems. in the f lo = f im / 4 mode, real or complex modulation can be used. the modulator multiplies successive input data samples by the sequence [1, 0, -1, 0] for a cos( t). the modulator modulates the input signal up to f im / 4, creating upper and lower images around f im / 4. the quadrature lo sin( t) is realized by delaying the cos( t) sequence by one clock cycle. using complex modula- tion, complex if is generated. the complex if combined with an external quadrature modulator provides image rejection. the sign of the lo can be changed to allow the user to select whether the upper or the lower image should be rejected (bit 1 of register 01h). when f im / 2 is chosen as the lo frequency, the input signal is multiplied by [-1, 1] on both channels. this pro- duces images around f im / 2. the complex image-reject modulation mode is not available for this lo frequency. the outputs of the modulator can be expressed as: in complex modulation, e +jwt in complex modulation, e -jwt where = 2 x x f lo . for real modulation, the outputs of the modulator can be expressed as: if more than one max5893 is used, their lo phases can be synchronized by simultaneously releasing reset . this sets the max5893 to its predefined initial phase. device reset the max5893 can be reset by holding the reset pin low for 10ns. this will program the control registers to their default values in table 2. during power-on, reset must be held low until all power supplies have stabi- lized. alternately, programming bit 5 of address 00h to a logic-high also resets the max5893 after power-up. it at t qt at t () = () () () = () () cos cos it at t bt t qt at t bt t () = () () + () () () = () () + () () cos sin sin cos ? ? it at t bt t qt at t bt t () = () () () () () = () () + () () ? cos sin sin cos ? ? 12-bit, 500msps interpolating and modulating dual dac with cmos inputs 24 ______________________________________________________________________________________ figure 13. (a) modulator in complex modulation mode; (b) modulator in real modulation mode sin( t) sin( t) cos( t) cos( t) i-channel input data to fir3 (a) q-channel input data i-channel output data q-channel output data (b) sin( t) sin( t) cos( t) cos( t) i-channel input data to fir3 q-channel input data i-channel output data q-channel output data
power-down mode the max5893 features three power-saving modes. each dac can be individually powered down through bits 2 and 3 of address 00h. the interpolation filters can also be powered down through bit 4 of address 00h, preserving the output level of each dac (the dacs remain powered). powering down both dacs will auto- matically put the max5893 into full power-down, includ- ing the interpolation filters. applications information frequency planning system designers need to take the dac into account during frequency-planning for high-performance appli- cations. proper frequency planning can ensure that optimal system performance is achieved. the max5893 is designed to deliver excellent dynamic per- formance across wide bandwidths, as required for communication systems. as with all dacs, some com- binations of output frequency and update rate produce better performance than others. harmonics are often folded down into the band of inter- est. specifically, if the dac outputs a frequency close to f s / n, the mth harmonic of the output signal will be aliased down to: thus, if n (m + 1), the mth harmonic will be close to the output frequency. sfdr performance of a current- steering dac is often dominated by third-order har- monic distortion. if this is a concern, placing the output signal at a different frequency other than f s / 4 should be considered. common to interpolating dacs are images near the divided clocks. in a dac configured for 4x interpolation this applies to images around f s / 4 and f s / 2. in a dac configured for 8x interpolation this applies to images around f s / 8, f s / 4, and f s / 2. most of these images are not part of the in-band (0 to f data / 2) sfdr specifi- cation, though they are a consideration for out-of-band (f data / 2 - f dac / 2) sfdr and may depend on the relationship of the dataclk to dac update clock (see the data clock section). when specifying the output reconstruction filter for other than baseband signals, these images should not be ignored. data clock the max5893 features synchronizers that allow for arbitrary phase alignment between dataclk and clkp/clkn. the dataclk causes internal switching in the max5893 and the phase between dataclk (input mode) to clkp/clkn will influence the images at dataclk. optimum image rejection is achieved when dataclk transitions are aligned with the falling edge of clkp. figure 14 shows the image level near dataclk as a function of the dataclk (input mode) to clkp/clkn phase at 500msps, 4x interpolation for a 10mhz, -6dbfs output signal. clock interface the max5893 features a flexible differential clock input (clkp, clkn) with a separate supply (av clk ) to achieve optimum jitter performance. it uses an ultra-low jitter clock to achieve the required noise density. clock jitter must be less than 0.5ps rms to meet the specified noise density. for that reason, the clkp/clkn input source must be designed carefully. the differential clock (clkn and clkp) input can be driven from a sin- gle-ended or a differential clock source. differential clock drive is required to achieve the best dynamic performance from the dac. for single-ended opera- tion, drive clkp with a low noise source and bypass clkn to gnd with a 0.1? capacitor. the clkp and clkn pins are internally biased to av clk / 2. this allows the user to ac-couple clock ff mf f nm n s out s == ? ? ? ? ? ? ? ? max5893 12-bit, 500msps interpolating and modulating dual dac with cmos inputs ______________________________________________________________________________________ 25 figure 14. effect of clkp/clkn to dataclk phase on f s / 4 images f s / 4 images vs. clkp/clkn to dataclk delay f data = 125mwps, 4x interpolation clkp/clkn delay (ns) image level (dbc) 6.0 4.0 2.0 -100 -90 -80 -70 -60 -50 -110 0 8.0 f s / 4 - f out f out = 10mhz a out = -6dbfs f s / 4 + f out
max5893 sources directly to the device without external resistors to define the dc level. the input resistance of clkp and clkn is 5k ? . a convenient way to apply a differential signal is with a balun transformer as shown in figure 15. alternatively, these inputs may be driven from a cmos-compatible clock source, however it is recommended to use sine-wave or ac-coupled differential ecl/pecl drive for best dynamic performance. output interface (outi, outq) the max5893 outputs complementary currents (outip, outin) and (outqp, outqn), that can be utilized in a differential configuration. load resistors convert these two output currents into a differential output voltage. the differential output between outip (outqp) and outin (outqn) can be converted to a single-ended output using a transformer or a differential amplifier. figure 16 shows a typical transformer-based applica- tion circuit for generation of if output signals. in this configuration, the max5893 operates in differential mode, which reduces even-order harmonics, and increases the available output power. pay close atten- tion to the transformer core saturation characteristics when selecting a transformer. transformer core satura- tion can introduce strong second harmonic distortion, especially at low output frequencies and high signal 12-bit, 500msps interpolating and modulating dual dac with cmos inputs 26 ______________________________________________________________________________________ figure 15. single-ended-to-differential clock conversion using a balun transformer single-ended iinput 1:1 ratio mini-circuits adtl1-12 24.9 ? 24.9 ? clkp clkn 100nf 100nf max5893 figure 16. differential-to-single-ended conversion using wideband rf transformers max5893 outqp outqn qdac 12 1:1 1:1 50 ? 100 ? 50 ? v qout , single-ended outip outin idac 12 1:1 1:1 50 ? 100 ? 50 ? v iout , single-ended
amplitudes. it is recommended to connect the trans- former center tap to ground. if a transformer is not used, the outputs must have a resistive termination to ground. figure 17 shows the max5893 output configured for differential dc-coupled mode. the dc-coupled configuration can be used to eliminate waveform distortion due to highpass filter effects. applications include communication systems employing analog quadrature upconverters and requir- ing a high-speed dac for baseband i/q synthesis. if a single-ended dc-coupled unipolar output is desir- able, outip (outqp) should be selected as the out- put, and connect outin (outqn) to ground. using the max5893 output single-ended is not recommended because it introduces additional noise and distortion. the distortion performance of the dac also depends on the load impedance. the max5893 is optimized for a 50 ? double termination. it can be used with a trans- former output as shown in figure 16 or just one 25 ? resistor from each output to ground and one 50 ? resis- tor between the outputs (figure 17). higher output ter- mination resistors may be used, as long as each output voltage does not exceed +1v with respect to gnd, but at the cost of degraded distortion performance and increased output noise voltage. reference input/output the max5893 supports operation with the on-chip 1.2v bandgap reference or an external reference voltage source. refio serves as the input for an external, low- impedance reference source, and as the output if the dac is operating with the internal reference. max5893 12-bit, 500msps interpolating and modulating dual dac with cmos inputs ______________________________________________________________________________________ 27 figure 17. the dc-coupled differential output configuration max5893 outqp outqn qdac 12 25 ? 50 ? 25 ? outip outin idac 12 25 ? 50 ? 25 ?
max5893 for stable operation with the internal reference, refio should be decoupled to gnd with a 1? capacitor. refio must be buffered with an external amplifier, if heavy loading is required, due to its 10k ? output resis- tance. alternatively, apply a temperature-stable external refer- ence to refio (figure 18). the internal reference is over- driven by the external reference. for improved accuracy and drift performance, choose a fixed output voltage ref- erence such as the max6520 bandgap reference. the max5893? reference circuit (figure 19) employs a control amplifier, designed to regulate the full-scale current i out for the differential current outputs of the dac. the output current can be calculated as: i outfs = 32 x i refio - 1lsb i outfs = 32 x i refio - (i out / 2 12 ) where i refio is the reference output current (i refio = v refio / r set ) and i out is the full-scale output current of the dac. located between fsadj and dacref, r set is the reference resistor, which determines the amplifier? output current for the dac. use table 5 for a matrix of different i outfs and r set selections. 12-bit, 500msps interpolating and modulating dual dac with cmos inputs 28 ______________________________________________________________________________________ figure 18. typical external reference circuit 1.2v reference current- source array dac refio external 1.25v reference r set fsadj i ref 10k ? dacref 1 f max5893 1.2v reference current- source array dac refio fsadj i ref 10k ? dacref 1 f max5893 r set full-scale current reference current r set ( ? ) output voltage i outfs (ma) i ref (?) calculated 1% eia std v ioutp/n * (mv p-p ) 2 62.50 19.2k 19.1k 100 5 156.26 7.68k 7.5k 250 10 312.50 3.84k 3.83k 500 15 468.75 2.56k 2.55k 750 20 625.00 1.92k 1.91k 1000 figure 19. max5893 internal reference architecture table 5. i outfs and r set selection matrix based on a typical 1.20v reference voltage * terminated into a 50 ? load.
max5893 12-bit, 500msps interpolating and modulating dual dac with cmos inputs ______________________________________________________________________________________ 29 power supplies, bypassing, decoupling, and layout grounding and power-supply decoupling strongly influ- ence the max5893 performance. unwanted digital crosstalk can couple through the input, reference, power-supply, and ground connections, which can affect dynamic specifications like signal-to-noise ratio or spurious-free dynamic range. in addition, electro- magnetic interference (emi) can either couple into or be generated by the max5893. observe the grounding and power-supply decoupling guidelines for high- speed, high-frequency applications. follow the power- supply and filter configuration guidelines to achieve optimum dynamic performance. using a multilayer printed circuit (pc) board with sepa- rate ground and power-supply planes, run high-speed signals on lines directly above the ground plane. since the max5893 has separate analog and digital sections, the pc board should include separate analog and digi- tal ground sections with only one point connecting the three planes at the exposed paddle under the max5893. run digital signals above the digital ground plane and analog/clock signals above the analog/clock ground plane. keep digital signals as far away from sensitive analog inputs, reference lines, and clock inputs as practical. use a symmetric design of clock input and the analog output lines to minimize 2nd-order harmonic distortion components, thus optimizing the dynamic performance of the dac. keep digital signal paths short and run lengths matched to avoid propaga- tion delay and data skew mismatches. the max5893 requires five separate power-supply inputs for the analog (av dd1.8 and av dd3.3 ), digital (dv dd1.8 and dv dd3.3 ), and clock (av clk ) circuitry. decouple each voltage supply pin with a separate 0.1? capacitor as close to the device as possible and with the shortest possible connection to the appropriate ground plane. minimize the analog and digital load capacitances for optimized operation. decouple all power-supply voltages at the point they enter the pc board with tantalum or electrolytic capacitors. ferrite beads with additional decoupling capacitors forming a pi-network could also improve performance. the exposed paddle (ep) must be soldered to the ground. use multiple vias, an array of at least 4 x 4 vias, directly under the ep to provide a low thermal and electrical impedance path for the ic. static performance parameter definitions integral nonlinearity (inl) integral nonlinearity is the deviation of the values on an actual transfer function from either a best straight-line fit (closest approximation to the actual transfer curve) or a line drawn between the end points of the transfer func- tion, once offset and gain errors have been nullified. for a dac, the deviations are measured at every indi- vidual step. differential nonlinearity (dnl) differential nonlinearity is the difference between an actual step height and the ideal value of 1 lsb. a dnl error specification of less than 1 lsb guarantees no missing codes and a monotonic transfer function. offset error the offset error is the difference between the ideal and the actual offset current. for a dac, the offset point is the average value at the output for the two midscale digital input codes with respect to the full-scale of the dac. this error affects all codes by the same amount. gain error a gain error is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. this error alters the slope of the transfer function and corresponds to the same percentage error in each step. dynamic performance parameter definitions settling time the settling time is the amount of time required from the start of a transition until the dac output settles its new output value to within the specified accuracy. noise spectral density the dac output noise is the sum of the quantization noise and thermal noise. noise spectral density is the noise power in 1hz bandwidth, specified in dbfs/hz. signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital samples, the theoretical maximum snr is the ratio of the full-scale analog output (rms value) to the rms quantization error (residual error). the ideal, theoretical maximum snr can be derived from the dac? resolu- tion (n bits): snr db = 6.02 db x n + 1.76 db
max5893 however, noise sources such as thermal noise, refer- ence noise, clock jitter, etc. affect the ideal reading. therefore, snr is computed by taking the ratio of the rms signal to the rms noise, which includes all spec- tral components minus the fundamental, the first four harmonics, and the dc offset. spurious-free dynamic range (sfdr) sfdr is the ratio of the rms amplitude of the carrier frequency (maximum signal components) to the rms value of their next largest distortion component. sfdr is usually measured in dbc and with respect to the car- rier frequency amplitude or in dbfs with respect to the dac? full-scale range. depending on its test condition, sfdr is observed within a predefined window or to nyquist. two-/four-tone intermodulation distortion (imd) the two-tone imd is the ratio expressed in dbc (or dbfs) of the worst 3rd-order (or higher) imd products to either output tone. adjacent channel leakage power ratio (aclr) commonly used in combination with wcdma (wide- band code-division multiple-access), aclr reflects the leakage power ratio in db between the measured pow- ers within a channel relative to its adjacent channel. aclr provides a quantifiable method of determining out-of-band spectral energy and its influence on an adjacent channel when a bandwidth-limited rf signal passes through a nonlinear device. 12-bit, 500msps interpolating and modulating dual dac with cmos inputs 30 ______________________________________________________________________________________
max5893 12-bit, 500msps interpolating and modulating dual dac with cmos inputs ______________________________________________________________________________________ 31 pin configuration 58 59 60 61 62 54 55 56 57 63 38 39 40 41 42 43 44 45 46 47 a7 a1 outip qfn top view outin gnd av dd3.3 gnd outqp outqn gnd av dd3.3 gnd 52 53 av dd1.8 dacref a2 dv dd1.8 a0 n.c. n.c. n.c. n.c. dataclk/b10 seliq/b11 b8 b9 b7 dv dd1.8 b6 sclk sdi sdo dv dd3.3 n.c. n.c. n.c. n.c. b0 b1 35 36 37 dv dd1.8 b2 b3 a8 a9 a10 a11 d vdd1.8 a4 a5 dataclk d vdd3.3 a6 n.c. n.c. n.c. clkn 48 cs clkp 64 gnd 65 66 67 av dd1.8 gnd av dd3.3 68 av clk 23 22 21 20 19 27 26 25 24 18 29 28 32 31 30 b5 b4 34 33 49 50 refio reset 51 fsadj 11 10 9 8 7 6 5 4 3 2 16 15 14 13 12 1 a3 17 max5893 exposed paddle
max5893 12-bit, 500msps interpolating and modulating dual dac with cmos inputs maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 32 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 68l qfn.eps c 1 2 21-0122 package outline, 68l qfn, 10x10x0.9 mm c 1 2 21-0122 package outline, 68l qfn, 10x10x0.9 mm

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